IV
Parallelism
Illustrated lecture notes
Unlock full chapter
↗
UNIT IV / ILP / 01
Instruction-level parallelism
⛶
Fullscreen
Jump to page
1. Instruction-level parallelism
2. What limits instruction overlap?
3. Throughput is not latency
4. The compiler packs two issue slots (locked)
5. A dependent pair needs different packets (locked)
6. One loop iteration fills some slots (locked)
7. Unroll four elements (locked)
8. Compare equal work (locked)
9. Issue first; execute when ready (locked)
10. How a waiting instruction wakes up (locked)
11. Register renaming follows the producer (locked)
12. Completed does not mean committed (locked)
13. Speculation and branch confirmation (locked)
14. Static schedule versus runtime selection (locked)
15. Independent work at different levels (locked)
16. Amdahl and the serial fraction (locked)
17. Instruction and data streams (locked)
18. SIMD and four lanes (locked)
19. MISD and MIMD (locked)
20. Two thread contexts share one core (locked)
21. SMT fills available slots (locked)
22. Two physical cores on one chip (locked)
23. Sharing a value between cores (locked)
24. A shared counter can lose an update (locked)
25. Independent work still needs an exchange (locked)
26. When extra cores stop helping (locked)
‹
›
✦ First 3 pages are open to everyone.
Request the full chapter →